NAND Flash Memory Chip Size Trend
Report No. FI-NFM-CST-0708, July 2008
NAND flash memories have historically doubled densities every year
with each new technology generation. This trend has been referred to
“Hwang’s Law”, named after Hwang Chang-gyu, former President of
Samsung Semiconductor who first coined the term. As NAND flash
memory encounters scaling challenges, it is becoming increasingly
difficult to maintain Hwang’s Law as chip sizes increase beyond
SLC (Single-Level-Cell) and MLC (Multi-Level-Cell) or 2-bit per cell
technologies are the current mainstream technologies. NAND flash
manufacturers are adopting 3-bit per cell and 4-bit per cell
technologies to reduce chip sizes and correspondingly, costs.
Three-bit per cell and 4-bit per cell NAND flash memory technologies
are expected to garner the majority of the market in four years.
NAND Flash Memory Chip Size Trend provides actual and estimated NAND
flash memory chip sizes and roadmaps for SLC, MLC, 3-bit per cell
and 4-bit per cell technologies by density, process technology
generation and vendor. The report covers NAND flash memory product
densities from 512Mb to 64Gb for Intel-Micron Flash Technologies,
Numonyx/Hynix, Samsung and SanDisk/Toshiba.